• Family Name: STM8L
• Core Processor: STM8
• Program Memory Type: 聽刀ROM
• Flash Size (Bytes): 16 kB
• RAM Size: 2 kB
• Speed: 16 MHz
• No of I/O Lines: 30
• InterfaceType / Connectivity:I2C / SPI費資 / USART
• Peripherals: On-Chip-DAC / On靜行-Chip-ADC / I2C / SPI / USART / Watchd對作og / PWM / Analog Com森靜parators
• Number Of Timers: 4
• Supply Voltage: 1.8 to 3.6 V
• Operating Temperature: -40 to +85 靜小°C
• On-Chip ADC: 22-chx12-bit
• On-Chip DAC: 1-chx12-吧樹bit
• Watchdog: 2

The STM8L151K4T6 device is a member of the ST多月M8L Ultralow power 8-bit family. The S家那TM8L15xxx family operates from 1.8 V了河 to 3.6 V (down to 1.65 V at po船花wer down) and is available in the -40 林人to +85 °C and -40 to +125 多來°C temperature ranges.

The STM8L151K4T6 Ultralow power family features the 自畫enhanced STM8 CPU core providin都房g increased processing power (up 秒坐to 16 MIPS at 16 MHz) while maint跳日aining the advantages of a CISC ar離下chitecture with improved c化高ode density, a 24-bit linear addressin船也g space and an optimized architecture 舊器for low power operations訊器.

STM8L151K4T6 Features:

• Operating conditions
  • Operating power supp山新ly range 1.8 V to 3.6 V (down to 飛什1.65 V at power down)
  • Temperature range: - 40 °C to 85 or 見一125 °C
• Low power features
  • 5 low power modes: Wait , Low power r靜他un (5.1 μA), Low power w北笑ait (3 μA), Active-halt with full RTC (影風1.3 μA), Halt (350 nA)
  • Dynamic consumption: 195哥東 μA/MHz+440 μA
  • Ultralow leakage per I/0:生機 50 nA
  • Fast wakeup from Halt: 4.7 μs
• Advanced STM8 core
  • Harvard architecture and 3-視文stage pipeline
  • Max freq. 16 MHz, 16 CISC MIPS答如 peak
  • Up to 40 external interrupt兵外 sources
• Reset and supply mana行購gement
  • Low power, ultrasafe BOR reset with 5 車農selectable thresholds
  • Ultralow power POR/PDR們媽
  • Programmable voltage d些商etector (PVD)
• Clock management
  • 1 to 16 MHz crystal os北業cillator
  • 32 kHz crystal oscillator
  • Internal 16 MHz factory-trimmed R時秒C
  • Internal 38 kHz low consu技長mption RC
  • Clock security system好對
• Low power RTC
  • BCD calendar with alarm inte花計rrupt
  • Auto-wakeup from Halt w/ peri你好odic interrupt
• LCD: up to 4x28 segm跳動ents w/ step-up converter
• Memories
  • Up to 32 KB of Flash program memory 也又and 1 Kbyte of data EEPROM with ECC, RW對山W
  • Flexible write and read protection mode器日s
  • Up to 2 Kbytes of RAM
• DMA
  • 4 channels; supported peripheral為山s: ADC, DAC, SPI, I2C, USART, timers
  • 1 channel for memory-關話to-memory
• 12-bit DAC with output buffer
• 12-bit ADC up to 1 Msps/25 channe音對ls
  • T. sensor and internal referen山是ce voltage
• 2 Ultralow power comparator民話s
  • 1 with fixed threshold and 1 慢兵rail to rail
  • Wakeup capability
• Timers
  • Two 16-bit timers wi近報th 2 channels (used as IC,弟視 OC, PWM), quadrature懂南 encoder
  • One 16-bit advanced c務月ontrol timer with 3 ch舊志annels, supporting motor cont北議rol
  • One 8-bit timer with 7-bit prescaler
  • 2 watchdogs: 1 Window, 1 Ind靜友ependent
  • Beeper timer with 1, 2 or 林訊4 kHz frequencies
• Communication interfaces
  • Synchronous serial interface銀對 (SPI)
  • Fast I2C 400 kHz SMBus and PMBus
  • USART (ISO 7816 interface and IrDA)
• Up to 41 I/Os, all mappable on inter時文rupt vectors
• Up to 16 capacitive sensing cha姐大nnels with free firmware
• Development support
  • Fast on-chip programmi請藍ng and non intrusive debugging w錢長ith SWIM
  • Bootloader using USART
• 96-bit unique ID